In System on a Chip (SOC) designs, an integrated circuit (IC) is designed by using automated tools. A circuit netlist is generated by using automated Electronic Design Automation (EDA) tools. The circuit netlist is a hierarchical transistor-level description of circuit building blocks and is used with leaf cells to design an IC. A leaf cell is a basic building block with one or more transistors that can be used in a design. The basic circuit building blocks, described in the netlist, are integrated onto a single integrated chip. These circuit building blocks include, but are not limited to, microprocessors, field-programmable gate arrays (FPGAs), memories, digital application-specific integrated circuits (ASICs), operational amplifiers (op-amps), linear regulators, phase-locked loops, oscillators and active filters. The IC design is rigorously characterized with respect to several design parameters, according to IC design rules, to ensure that circuit-building blocks operate in the expected manner in the IC design. These design parameters include, but are not limited to, the timing parameter and the power parameter.
In traditional methods for characterizing the design parameters of an IC design, the circuit netlist file provides a description of the circuit building blocks, their connections, and some of their attributes. The circuit netlist file includes a symbolic representation of the circuit building blocks. Further, the circuit designer has to describe the circuit building blocks for every unique IC design. Therefore, a need exists for a method and system for characterizing an IC design wherein the circuit netlist can be easily modified by a user during the design cycle. There also exists a need for developing a method and system for generating a generic/parameterized description of circuit-building blocks that can be used in different IC designs.